1. Field of the Invention
The present invention relates generally to electronic latches.
2. Description of the Related Art
A variety of modern signal-conditioning systems require electronic latches which can be latched to indicate the state of a fluctuating input signal at a selected latch time. Because these systems often process complementary metal-oxide-semiconductor (CMOS) signals and generally include a significant number of latches which operate at high speeds, there is a continuing search for latch structures that provide CMOS-level latch signals but enhance latch speed and reduce current drain.
The present invention is directed to latch structures and systems that realize enhanced latch speed and reduced latch current drain while providing CMOS-level latch signals. These goals are realized with bipolar junction structures and CMOS structures that are arranged to limit latch currents in response to CMOS-level sense signals Ssns.
The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.